• 专利附录
  • 专利说明
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    • 专利摘要:
    The detection circuit comprises a detector (1) connected to an integration node (N). A polarization circuit (5) polarizes the detector (1) between a first polarization state and a second floating state. The potential of the retention node (N) is at a target value when the bias circuit polarizes the detector in the first state and evolves when the detector is in the floating state. A measurement circuit without loss of load delivering a value representative of the potential present on the integration node N. An electric charge transfer circuit for moving the electrical charges from a parasitic capacitor (CPD) of the photodiode (1) to a integration capacitor (CINT). An output terminal delivers a voltage representative of the potential present on the second terminal of the first capacitor (CINT).
    公开号:FR3059189A1
    申请号:FR1661322
    申请日:2016-11-21
    公开日:2018-05-25
    发明作者:Sebastien Aufranc；Eric Sanson
    申请人:Societe Francaise de Detecteurs Infrarouges SOFRADIR SAS；
    IPC主号:
    专利说明:

    Holder (s): SOCIETE FRANÇAISE DE DETECTEURS INFRAROUGES - SOFRADIR Simplified joint-stock company.
    Extension request (s)
    Agent (s): CABINET HECKE Société anonyme.
    LOW FLOW AND LOW NOISE DETECTION CIRCUIT.
    FR 3 059 189 - A1 f5 / j The detection circuit includes a detector (1) connected to an integration node (N). A polarization circuit (5) polarizes the detector (1) between a first polarization state and a second floating state. The potential of the retention node (N) is at a target value when the bias circuit polarizes the detector in the first state and evolves when the detector is in the floating state. A measurement circuit without loss of charge delivering a value representative of the potential present on the integration node N. A circuit for transferring electrical charges to move the electrical charges from a parasitic capacitor (C PD ) from the photodiode (1) to an integration capacitor (C | NT ). An output terminal delivers a voltage representative of the potential present on the second terminal of the first capacitor (C | NT ).
    Low-noise, low-noise detection circuit
    Technical field of the invention
    The invention relates to a detection circuit.
    State of the art
    Optical detection circuits generally include a photodetector coupled to a read circuit. The function of the read circuit is to convert and possibly amplify the signal from the photodetector so that it can be processed.
    FIG. 1 represents an example of a detection circuit commonly used with photodetectors. The circuit comprises a photodetector 1 and a reading circuit 2. A terminal of the photodetector 1, the cathode in the example of FIG. 1, is connected to the reading circuit 2. The other terminal of the photodetector 1, the anode by example, is connected to the potential of the substrate of the photodetector V SU b25 The read circuit 2 can be of the integrator type. It has two functions: on the one hand, it integrates the current h of the photodetector 1 and thus converts the current into an exploitable voltage V s , and on the other hand, it ensures the polarization of the photodetector 1. By way of example, the reading circuit 2 can be produced by a capacitive transimpedance amplifier (“Capacitive
    Transimpedance Amplifier "in English, CTIA) represented in FIG. 1. Such an integrator comprises an operational amplifier 3. The first input of the amplifier 3, the negative input, forms the input of the read circuit 2 and the output of the amplifier 3 forms the output of the reading circuit 2. The second input of the amplifier, the positive input in the example of FIG. 1, receives a reference potential V RE f · The reading circuit 2 also includes an integration capacity C1 and a reset switch S1 connected in parallel between the first input of the amplifier and the output of the amplifier. The output of the read circuit 2 delivers the voltage V s representative of the received signal.
    io This embodiment is particularly effective for the detection and management of medium or weak optical signals, but this efficiency is obtained at the expense of space and consumption. It also turns out that when the photodetector receives a light flux of very low intensity, the signal to noise ratio is degraded by the emission of parasitic photons emitted by the amplifier implanted in the pixel and it is very difficult to obtain interesting performances.
    In order to obtain very sensitive sensors, the detection circuit is produced in a particular way by means of an architecture of the SFD type (Source
    Follower per Detector) illustrated in Figure 2. This type of sensor works with low radiation conditions, that is to say with a low incident flux.
    As in conventional detectors, the incident radiation is converted into an amount of electrons which is representative of the scene observed. For this type of sensor, it is important to limit the electronic noise generated by the detection circuit, that is to say the amount of electrons which is not linked to the scene observed. A first way to reduce the amount of parasitic electrons is to limit the electrical consumption of the circuit, which encourages simplification of the detection circuit.
    The integration of the charges emitted by the photodetector is then carried out by the internal capacitor of the photodetector.
    As illustrated in Figure 2, the detection circuit includes a photodiode
    1 with its internal capacitor Cpd. The circuit also includes a reset transistor T1 which makes the connection between the photodetector 1 and a bias voltage Vreset. The switching of the reset transistor T1 between a conducting state and a blocking state makes it possible to switch the photodiode 1 between a reverse bias and a floating state.
    When photodiode 1 is in the floating state, the electrical charges generated are stored in the parasitic capacitor Cpd. As the electric charges are stored in the capacitor Cpd, the voltage across the terminals of the photodiode 1 changes. This change in polarization conditions also results in a degradation of the integrity of the signal, for example with a change in the conversion rate of the electromagnetic radiation received into a quantity of electrons, by the change in the value of the capacitance of the capacitor. Cpd, or by increasing the stray leakage current in the detector.
    The photodiode 1 is also connected to a processing circuit 4 which processes the signal emitted by the photodiode 1.
    The charges generated by photodiode 1 are partly stored by the internal capacitor Cpd of photodiode 1, which results in an evolution of the potential of the integration node N connected to the processing circuit 4. The electrical capacity of the integration node N partly comes from the electrical capacitance of photodiode 1 and partly from the parasitic capacitances of the other elements connected to the integration node N.
    However, in this architecture, there is always a high level of noise in terms of electrons in low flux detectors. Furthermore, these architectures have a low linearity in the conversion of the light signal into an electrical signal because the detection is carried out by leaving the photodetector at a floating potential which evolves as the capacitor Cpd charges. This non-linearity as well as the loss of signal integrity limits the amplitude of the signal and therefore the number of charges that can be stored, which limits the signal to noise ratio. This problem is particularly important for detectors which tolerate little variation in their bias potential, for example infrared LWIR band detectors.
    Subject of the invention
    It can be seen that there is a need to provide a detection circuit which makes it possible to obtain a better correlation between the received optical signal and the generated electrical signal.
    We tend to fill this need by means of a circuit which includes:
    - a detector having a parasitic capacitor and configured to deliver electrical charges according to an observed phenomenon,
    - a bias circuit configured to bias the detector during a first period and leave a first terminal of the detector at a floating potential during a second period.
    The circuit is remarkable in that it includes:
    - A first capacitor having a first terminal connected to the first terminal of the detector to form a retention node with the parasitic capacitor, the retention node being at a target value during the first period and evolving during the second period.
    a circuit for transferring electrical charges from the parasitic capacitor to the first capacitor, the circuit for transferring electrical charges being configured to polarize a second electrode of the first capacitor so as to shift the potential of the retention node towards the target value,
    an output terminal delivering a voltage representative of the potential present on the second terminal of the first capacitor.
    io Brief description of the drawings
    Other advantages and characteristics will emerge more clearly from the description which follows of particular embodiments of the invention given by way of nonlimiting examples and represented in the appended drawings, in which:
    FIG. 1 schematically represents a detection circuit of the capacitive transimpedance amplifier type,
    FIG. 2 schematically represents a detection circuit of the SFD type,
    FIG. 3 schematically represents a particular embodiment of a detection circuit according to the invention,
    - Figure 4 shows, schematically, several detection circuits according to the invention in relation to a detection matrix.
    Description of preferred embodiments of the invention
    As illustrated in FIG. 3, the detection circuit partly takes up the SFD (Source-Follower per Detector) type assembly. The detection circuit includes a photodetector 1 which is preferably a photodiode. The photodetector 1 is associated with a polarization circuit 5. The polarization circuit 5 makes it possible to polarize the photodetector 1 between first and second different states according to first and second periods.
    During the first period, the photodetector 1 is in the first state, the photodetector 1 is advantageously reverse biased. During the second period, the photodetector is in the second state, the photodetector 1 is left in a floating state where the initial polarization, for example the reverse polarization, evolves as a function of the accumulation of the charges received, here the evolution is towards direct polarization. The acquisition of the electromagnetic signal is carried out when the photodetector 1 is in the second state, that is to say during the second period. The floating state is achieved by leaving the electrode connected to the bias circuit 5 at a floating potential.
    In the embodiment illustrated in FIG. 3, the photodetector 1 is represented schematically as a current source because it delivers electrical charges as a function of the electromagnetic radiation received. Photodetector 1 can be a photodiode, a quantum well or quantum well device, or any other detector that is configured to transform incident electromagnetic radiation into electrical charges.
    In the embodiment illustrated in FIG. 3, the bias circuit 5 is produced in a compact manner by means of a switch T1 which connects a source of bias voltage Vreset to a first electrode of the photodetector 1. By flipping the switch T1 between the passing and blocking states, it is possible to switch the photodetector 1 between a reverse bias state and a floating state. In a particularly compact embodiment, the switch T1 is formed by a transistor and advantageously by a field effect transistor. The control electrode of transistor T1 is connected to a control circuit A, for example a signal generator which transmits the signal RSEL Rn . Depending on the received signal, the switch T1 switches between passing and blocking states and the photodetector 1 switches between reverse polarization and a floating state. The second electrode of the photodetector 1 is connected to a voltage source which delivers the voltage Vdet. The RSEL signal Rn makes it possible to define the first and second periods.
    The detection circuit comprises a retention node N formed by the connection between the first electrode of the photodetector 1 and the first electrode of a first capacitor also called integration capacitor Cint- In other words, the retention node N is formed by the parasitic capacitor Cpd and the integration capacitor Cint- The retention node N is also connected to the bias circuit 5.
    During the acquisition period, that is to say the second period, the photodetector 1 is in its floating state, that is to say that it is connected to the capacitive retention node N which stores the electrical charges generated by the photodetector. The photodetector 1 transforms light radiation into electrical charges which are stored in the parasitic capacitor Cpd and also in the integration capacitor Cint. The accumulation of electrical charges in these two capacitors will lead to an evolution of the potential of the capacitive retention node N. When the bias circuit 5 places the photodetector 1 at a floating potential, the node N sees its potential evolving as the electric charges are generated and stored in the capacitors Cpd and Cint As indicated above, as and As the polarization of the retention node N changes, the polarization conditions of the photodetector 1 change which can, beyond a certain threshold, degrade the integrity of the signal.
    In other words, for the same instantaneous optical signal received, the photodetector 1 can generate different quantities of electrical charges according to its polarization state.
    This deterioration in signal integrity makes it more difficult to compare two quantities of electrons stored on the retention node N quantitatively. So as to be able to more easily compare two pieces of information stored on the retention node N, the device comprises a circuit for modulating the supply conditions of the photodetector 1 while the latter is at a floating potential, that is to say during the second period.
    The modulation circuit is configured to return the photodetector 1 to its initial state of polarization without eliminating the electrical charges generated or at least to bring the photodetector closer to its initial state defined during the first period. The polarization conditions at the terminals of the photodetector being more stable over time, it is then easier to compare two electrical signals to compare two optical signals quantitatively.
    Advantageously, the polarization modification across the terminals of the photodetector 1 is effected by a transfer of at least part of the electrical charges stored in the capacitor Cpd to the integration capacitor Cint- Whereas in the prior art, the charges electrics are eliminated to return to the initial state of polarization, in this embodiment, the electric charges are transferred to avoid the introduction of parasitic electric charges. Charges are transferred during the acquisition period.
    The detection circuit advantageously comprises a transfer circuit 6 configured to transfer electrical charges from the capacitor
    Cpd to the integration capacitor Cint- The charge transfer makes it possible to remove at least part of the charges accumulated in the parasitic capacitor Cpd and to transfer them to the capacitor Cint- The displacement of the charges generated and stored in the capacitor Cpd allows limit the fluctuations in the polarization conditions of the photodetector 1. In this way, for the same optical signal, the photodetector 1 generates substantially the same amount of electrical charge over a longer period of time and it is easier to compare the signals quantitatively received.
    The transfer circuit 6 is advantageously configured to block the transfer of electrical charges when the potential of the retention node reaches a predefined value. Advantageously, this predefined value is equal to or close to the target value defined during the first period.
    The charges are moved inside the retention node N by moving the charges between its different capacitive components.
    The displacement of the electrical charges from the capacitor Cpd to the capacitor Cint is done by injecting electrical charges into the second electrode of the capacitor Cint- For example, the displacement of the electrical charges is done by modifying the polarization of the second electrode of the capacitor Cint, for example by applying a voltage to the second electrode.
    Compared to an embodiment where a fixed number of electrical charges is transferred from the capacitor Cpd to the capacitor Cint each time the transfer circuit 6 is activated, it is advantageous to transfer all the electrical charges stored so as to replace the photodetector 1 under predefined conditions and preferably under polarization conditions closer to the start of the acquisition period.
    It is then advantageous to use a circuit 7 for measuring the potential value of the retention node N which is configured to measure the potential value of the retention node N.
    This particular architecture makes it possible to measure the potential value of the retention node N. It is then possible to initiate and / or stop the transfer of the electrical charges from the capacitor Cpd to the integration capacitor Cint as a function of the value of potential of the retention node
    NOT.
    The transfer may possibly be conditioned on the fact that the potential of the retention node N reaches a threshold value measured by the measurement circuit 7.
    By replacing the retention node N to a target value which is close to the conditions defined during the first period, the photodetector 1 will also be replaced in polarization conditions close to those defined by the first period. If several transfers are carried out during the second period, using a constant or substantially constant target value increases the repeatability of the measurements.
    In a particular embodiment, the circuit 7 for measuring the potential value of the retention node N can be activated before the circuit 6 for transferring electrical charges. In this way, the measurement circuit 7 will measure the value of the potential at node N and if the latter reaches a threshold value this triggers the transfer of electrical charges from the capacitor Cpd to the capacitor Cint- During the transfer of the charges, the circuit 7 measurement can be active and it measures the potential of the retention node N. The measurement circuit 7 stops the transfer of electrical charges when the potential of the retention node N reaches the target value.
    In a preferred variant, the circuit 7 for measuring the potential value of the retention node N and the circuit 6 for transferring the electric charges are activated simultaneously so that the transfer of the charges takes place until the potential of the node N reaches the target value.
    In a particular embodiment, the measurement circuit 7 includes a transistor T2 mounted as a follower so that the potential of the retention node
    N modulates the voltage delivered by transistor T2. The retention node N is connected to the control electrode of the transistor T2.
    The transistor T2 is advantageously a field effect transistor so that the retention node N is completely electrically isolated from the other elements of the circuit. This electrical insulation makes it possible to prevent electrical charges from being lost from node N or injected into node N, which avoids introducing a deviation from what has actually been detected by the photodetector. The generated signal is no longer distorted and a better correlation between the received optical signal and the electrical signal can be obtained. In other words, the signal is less degraded than in the circuits of the prior art.
    The electric charges generated by the photodetector 1 cannot be lost because the retention node N is completely isolated from the other elements of the circuit, that is to say by the insulating layer forming the integration capacitor Cint, by the gate insulator of transistor T2 and by the insulators of the capacitors.
    The retention node N is connected to the measurement circuit 7 so that the latter delivers information representative of the potential to the node N. According to the embodiments, the circuit 7 can be configured to deliver digital information or analog information.
    This information is delivered to the transfer circuit 6 to initiate and / or block the transfer of electrical charges.
    By way of example illustrated in FIG. 3, the voltage delivered by the transistor T2 evolves in analog fashion with the potential value of the retention node N. If a voltage represented in digital form is sought, it is possible to connect in output of transistor T2, an analog-digital converter which will deliver digital information representative of the measured value.
    The transfer circuit 6 can be produced in different ways. In one case, the activation and stopping of the transfer circuit are linked to the emission of signals by the measurement circuit 7 which transmits signals of the ON / OFF type. The measurement circuit 7 can emit an activation signal of the transfer circuit 6 as long as the potential of the node N does not reach the target value.
    In other cases, the signals emitted by the measurement circuit 7 are representative of the potential of the node N, which allows the transfer circuit 6 to make the node N converge more easily on the target value.
    Advantageously, the signal emitted by the measurement circuit 7 is analyzed in real time in order to apply a voltage to the second electrode of the capacitor Cint and to make the node N converge towards the target value.
    In other cases, the signals emitted by the measurement circuit 7 are analyzed and the analysis of these signals makes it possible to modulate a charge or a current towards the second electrode of the capacitor Oint3059189
    In the preferred embodiment illustrated in FIG. 3, the transfer circuit 6 includes an amplifier 8 and the voltage delivered by the transistor T2 is applied to the input of the amplifier 8. The other input of the amplifier 8 , is connected to a voltage source which delivers a voltage Vamp, here the voltage Vamp is advantageously offset from the voltage Vreset by a value equal to the threshold voltage of the transistor T2. The transfer circuit 6 is also configured to deliver the voltage value which makes it possible to transfer the charges from detector 1 and its stray capacitance Cpd to the capacitor Cint10
    In this way, when the transfer circuit 6 receives information indicating that the node N has moved away from the target value, the amplifier 8 delivers the signal to be applied to transfer the charges from Cpd to Cint and the transfer circuit 6 apply this signal to the capacitor Cint- The second electrode of the capacitor Cint charges until the electrical charges stored in the capacitor Cpd are transferred to the capacitor Cint and the potential of node N returns to the initial potential. At this time, the measurement circuit delivers information, for example a voltage, indicating that the node N is at the target value and the output of the transfer circuit 6 stabilizes at the value representative of the received signal, and stops charging the capacitor Cint- The value representative of the received signal is available on the output OUT of transfer circuit 6. The transfer circuit 6 can be stopped and the electrical charges accumulated in the second electrode of the capacitor Cint are preserved and the retention node N can again be charged with the new electrical charges generated by the photodetector 1.
    Advantageously, the amplifier 8 is formed by an operational amplifier. In this way, the output of the amplifier 8 is looped back into integrator mode and delivers at the output a voltage suitable for converging the voltage delivered by the transistor T2 towards the voltage Vamp, that is to say converging the node N towards its initial value. This embodiment is particularly advantageous because it makes it possible to connect the output of comparator 8 directly to the second electrode of the capacitor Cint and to have at the same time a signal representative of the optical signal at the output of the same amplifier.
    In the case where the amplifier 8 is formed by an operational amplifier, it is advantageous to carry out the resetting of the second electrode of the capacitor Cint by short-circuiting the output terminal of the amplifier 8 ïo with its terminal input connected to the measurement circuit 7. The short circuit can be achieved by means of a switch which receives the signal S res on its control electrode and from a signal generator.
    Alternatively, the measurement circuit or the transfer circuit can be configured to deliver information representative of the difference between the potential value measured at the retention node N and the target value or a value representative of the target value. This information representative of the difference is used to define the voltage variation to be applied to the second terminal of the capacitor Cint or the quantity of electrical charges to be applied to the second electrode of the capacitor Cint, although the transfer circuit 6 is illustrated in a configuration with an amplifier which is particularly advantageous to facilitate the conversion to the target value, it is also possible to use a comparator to charge the capacitor Cint In an embodiment illustrated in FIG. 3, the measurement circuit 7 is configured to deliver a voltage representative of the charges received by the detector 1 and stored on the node N. In fact, when the voltages have converged, the node N is at its initial value which is known, and the charges of the detectors are all transferred to the capacitor Cint, the second electrode of the capacitor Cint is then at a potential repr sentative of the charges from the detector, and this potential is the same as the output OUT.
    In another particular embodiment illustrated in FIG. 3 and which can be combined with the other embodiments described above, the second electrode of the capacitor Cint is connected to an additional capacitor also called memory capacitor Cm.
    The second electrode of the capacitor Cint is connected to the first electrode of a memory capacitor Cm. The second electrode of the memory capacitor Cm is connected to a second reference voltage source, here the voltage V RE f · The second reference voltage source delivers a fixed potential.
    It is advantageous to use the memory capacitor Cm so as to memorize the voltage applied by the circuit 6 when the latter charges the capacitor Cint, and to keep this voltage on the second electrode of the capacitor Cint- In the embodiment of In FIG. 3, this information can be stored by placing the switch T4 in the open state and for example by stopping the circuit 6. In this way, the voltage present on the second electrode of the capacitor Cint can be maintained longer and more precisely, this makes it possible to stabilize the potential of the node N and therefore to reduce its evolution during the acquisition period. The charges stored on the capacitor Cm are not necessarily representative of the electrical charges generated by the photodetector.
    By charging the second electrode of the capacitor Cint, the first electrode of the capacitor Cm is also charged. In this way, the voltage present on the second electrode of the capacitor Cint can be maintained longer.
    The sum of the electric charges generated by the photodetector 1 is stored in the parasitic capacitor Cpd then in the integration capacitor Cint as and when transfers. When the circuit 6 has transferred the electrical charges to the capacitor Cint, the voltage present on the second electrode of the capacitor Cint is representative of all the electrical charges generated and therefore of the optical signal received io throughout the acquisition period.
    When the circuit 6 has transferred the electrical charges to the capacitor Cint, the second terminal of the capacitor Cint is connected to the output of the detection circuit so as to deliver a signal representative of the optical signal received. The output of the detection circuit can be connected to an analysis circuit (not shown).
    Preferably, the target value for the node N corresponds to the value of the potential of the node N when the photodetector 1 is in the first state. In the embodiment illustrated in Figure 3 and particularly advantageous because compact, the voltage Vamp applied to the positive input of the operational amplifier 8 is equal to the voltage Vreset offset by the value of the threshold voltage of the transistor T2 when this transistor is in follower mode. In this way, the circuit 6 is configured so that the voltage applied to the second electrode of the capacitor Cint replaces the retention node N at the potential Vreset as would the bias circuit 5 during initialization of the photodetector 1.
    Although the detection circuit can carry out the continuous transfer of the charges generated by the photodetector 1, it is particularly advantageous to carry out the transfer of the electric charges periodically, that is to say with alternating transfer phases and phases accumulation.
    By periodically measuring the value of the potential present on the retention node N and by transferring the stored electrical charges, it is possible to avoid that the polarization conditions of the photodetector 1 fluctuate significantly. It is then possible to quantitatively compare the optical signals received by comparing the stored electrical signals.
    In order to limit the electrical consumption of the detection circuit, it is particularly advantageous not to measure the potential of the retention node N continuously but preferably periodically. The same applies to the transfer of electric charges from the capacitor Cpd to the integration capacitor Cint. In an embodiment which is particularly advantageous since it is compact, in order to facilitate the implementation of these actions periodically, the circuit advantageously includes a switch T3 which is connected between the output of the circuit 7 for measuring the potential of the retention node N, formed here by the transistor T2 and the input of the transfer circuit 6. In the embodiment of FIG. 3, more particularly, the switch T3 connects the output of the transistor T2 to the first input of the amplifier 8.
    If the measurement of the potential at node N and / or the transfer of electrical charges are carried out periodically, it is possible not to supply these measurement and transfer circuits when they are not in use. A gain in electrical consumption is then obtained. This reduced consumption makes it possible to reduce the stray photonic emission and to improve the integrity of the received optical signal.
    If the charge transfer is carried out at least once and preferably periodically, the acquisition period can be broken down into at least two distinct phases. In a first phase also called integration phase, the optical signal received by the photodetector generates electric charges which are stored in the capacitor Cpd and in the capacitor Cint- In this first phase, the switches T3 and T4 are in the state blocking, i.e. open. The potential of the retention node ίο N evolves as the electrical charges are stored.
    In the second phase, also called transfer phase, the switches T3 and T4 are in the on state, that is to say closed. The potential of the node N is measured and a voltage is applied to the second electrode of the capacitor Cint so that the potential of the retention node N is for example equal to the target value. During the two phases of the acquisition period, the photodetector 1 is in the floating state and it generates electrical charges as a function of the optical signal received.
    As indicated above, according to the embodiments, the switches T3 and T4 can be toggled simultaneously by receiving the same signal on their control electrode. This case is illustrated in FIG. 3 where the switches T3 and T4 receive the same signal SEL Rn . It is also possible to provide that the switches T3 and T4 receive different signals, the independent and adapted commands of T3 and T4 allow for example to reduce the disturbances on the node N during the switching operations. The transistor T4 can be actuated logically between passing and blocking states. However, it is particularly advantageous to define at least two pass-through states, one of the states of which limits the amount of current which can pass through the transistor. This precaution makes it possible to avoid too sudden transitions of electric charges which has the effect of degrading the integrity of the signal.
    By applying, on the second terminal of the capacitor Cint, the voltage necessary for the potential of the retention node N to return to its initial conditions or to approach its initial conditions, i.e. its polarization at the start of the acquisition period, the charges of the retention node N present on the parasitic capacitor Cpd are moved to the integration capacitor Cint10
    The displacement of the charges makes it possible to replace the integration node N in a level of polarization identical or substantially identical to that of the beginning of the period of acquisition which makes it possible to replace the photodetector in a state of polarization identical or almost identical to that of the start of the acquisition period.
    As the transfer cycles progress, the number of electrical charges stored in the capacitor Cint increases. The voltage present on the second electrode of the capacitor Cint at the end of the second period is representative of the total number of electrical charges generated by the photodetector during the acquisition period.
    FIG. 3 illustrates a detection circuit with a single photodetector 1. To form a detection matrix, it is possible to form a plurality of detection devices arranged in the form of a matrix and identical to what is presented for the figure 3. The detection matrix comprises a plurality of detection circuits as presented above. The detection circuits are organized in rows and columns.
    It is particularly advantageous to provide that the bias circuits 5 of the detection circuits receive the same first synchronization signal (RSELrn). In this way, the first periods and the second periods are synchronized for the detection matrix.
    The bias circuits 5 of a line or of a column of detection circuits are connected to a control circuit A configured to perform a simultaneous switching between the first period and the second period.
    The detection matrix is formed by a plurality of detection circuits which are organized according to one or more repetition steps in one or two directions of organization, for example according to the columns and the rows.
    In one embodiment, the detection matrix is divided into pixels formed by the detectors associated with the bias circuit 5, the integration capacitor Cint and the measurement circuit 7. The pixels are organized according to one or more repetition steps in one or two directions of organization, for example according to the columns and the rows.
    The detection matrix is surrounded by an area devoid of a detector. This detector-free area has a width at least equal to the width of a pixel, preferably a width at least equal to two pixels. The area without detector is in the form of a ring having a width equal to at least one repetition step, preferably at least equal to two repetition steps.
    In a particularly advantageous embodiment since it is compact, the circuit 6 is offset outside the photodetector array, this makes it possible to eliminate the space requirement of this function on the area of the circuit most constrained in terms of available surface, and therefore increasing the compactness of the photodetector array. In addition, this removes the main source of parasitic photonic emission from the photodetector array and thus improves the integrity of the received optical signal. The photodetector array is devoid of transfer circuit 6. The transfer circuit 6 or at least the amplifier 8 of the transfer circuit 6 is spaced from the nearest photodetector by a distance at least equal to a repetition step and preferably at least two repetition steps.
    The transfer circuit 6 is offset from the detection matrix so as to reduce or even eliminate the disturbances linked to the operation of the transfer circuit 6 and more particularly to the operation of the amplifier 8. This offset of the transfer circuit makes it possible to reduce the io noise level in the detection circuits.
    In a particularly advantageous embodiment since it is compact, the circuit 6 is shared between Np photodetectors, this makes it possible to divide by Np the size of this function in the detection matrix and therefore to increase the compactness.
    As a variant, the circuit 6 for transferring electric charges may be common to several detection circuits of a row or of a column. Figure 4 illustrates a pooling for a column.
    If the transfer circuit 6 is common to several detection circuits, the different second electrodes of the capacitors Cint and therefore the different output terminals are connected to the same transfer circuit 6. So that the polarization of a capacitor Cint is associated with the retention node N of the same pixel, the circuit advantageously includes a switch T4 which is connected between the second electrode of the integration capacitor Cint and the transfer circuit 6.
    The control circuit and the transfer circuit 6 are configured to sequentially transfer the charges from the retention nodes N of said detection circuits during the second period. In this way, sequentially, during the second period, the electric charges present in the retention nodes are displaced.
    Advantageously, each detection device comprises a transistor T3 and a transistor T4 which are turned on or off depending on whether the detection device is in the transfer phase or in the integration phase of the acquisition period, c is the second period.
    By way of example, the column is formed by n detection devices io representative of n rows of the matrix.
    When the switches T3 and T4 of a first detection device are in the on state, the other switches T3 and T4 are in the blocking state. In this way, each of the retention nodes N in the column can be analyzed alone without risk of disturbing the other retention nodes in the column.
    The signal SELRn can therefore be an activation signal of the switches T3 and T4 of the device of row n of the column or more generally of all the switches T3 and T4 of row n of the detection matrix.
    In the illustrated embodiment, the same connection is used to connect the output of the amplifier 8 with all the switches T4 of the same column. Activating the different switches T4 sequentially makes it possible to vary the potential of only one node N at a time.
    In the matrix, it is advantageous to connect all the input terminals of the transfer circuits 6 to the same polarization source connected to the voltage Vdd by means of a switch T5 selecting the sought column. The switch T5 receives on its control electrode the signal SEL Cn . In this way, it is possible to select the transfer circuits of one column without selecting the transfer circuits of the other columns.
    It is also advantageous to place a transistor T6 between the voltage Vdd and the switch T5 in order to modulate the polarization conditions of the transistor T2 in follower mode.
    This architecture of the detection device is particularly advantageous in the field of detection of weak flux signals and more particularly in the field of astronomy where the collected signals are very weak.
    While many works are carried out on the architecture of photodetectors in order to improve the integrity of the signal on the one hand, and to extend the dynamics of the received signal on the other hand on detectors with little tolerance for polarization variations, detection device makes it possible to obtain results superior to the two architectures known from the prior art, SFD and CTIA.
    The photodetector can be a photodetector configured to detect visible or infrared radiation. In the infrared domain, the photodetector to be configured to detect at least one spectral band among the VLWIR, LWIR, MWIR and SWIR bands.
    In the infrared domain and more particularly in the LWIR band, the detection device makes it possible to maintain the integrity of the signal over a larger operating range in comparison with the architectures of the prior art.
    Although the detection circuit is presented with a photodetector, it is also of interest for all detectors which deliver an electrical signal according to an external stimulus, for example a pressure sensor.
    权利要求:
    Claims (18)
    [1" id="c-fr-0001]
    Claims
    1. Detection circuit comprising:
    - a detector (1) having a parasitic capacitor (Cpd) and configured to deliver electrical charges according to an observed phenomenon,
    - a polarization circuit (5) configured to polarize the detector (1) during a first period and leave a first terminal of the detector (1) at a floating potential during a second period, circuit characterized in that it comprises
    - a first capacitor (Cint) having a first terminal connected to the first terminal of the detector (1) to form a retention node (N) with the parasitic capacitor (Cpd), the retention node (N) being at a value target during the first period and evolving during the second period,
    - a circuit (6) for transferring electrical charges from the parasitic capacitor (Cpd) to the first capacitor (Cint), the circuit (6) for transferring electrical charges being configured to polarize a second electrode of the first capacitor (Cint) of so as to shift the potential of the retention node (N) towards the target value and to block the transfer of electrical charges when the potential of the retention node reaches a predefined value,
    - an output terminal delivering a voltage representative of the potential present on the second terminal of the first capacitor (Cint) ·
    [2" id="c-fr-0002]
    2. Circuit according to claim 1, characterized in that it comprises a measurement circuit (7) configured to measure the potential of the retention node (N) and in that the measurement circuit (7) delivers information representative of the potential of the retention node (N) to the transfer circuit (6) so that the transfer circuit (6) delivers a voltage configured to transfer the electric charges from the parasitic capacitor (Cpd) to the first capacitor (Cint) ·
    5
    [3" id="c-fr-0003]
    3. Circuit according to claim 2, characterized in that the measuring circuit (7) comprises a follower transistor (T2) having a control electrode connected to the retention node (N) so as to modulate the voltage delivered by the follower transistor (T2) as a function of the potential of the retention node (N).
    [4" id="c-fr-0004]
    4. Circuit according to claim 3, characterized in that the output of the follower transistor (T2) is connected to the transfer circuit (6) and in that the transfer of electrical charges from the parasitic capacitor (Cpd) to the first capacitor ( Cint) is stopped when the follower transistor (T2)
    15 delivers a voltage representative of the target value.
    [5" id="c-fr-0005]
    5. Circuit according to any one of claims 2 to 4, characterized in that the transfer circuit (6) comprises an amplifier (8) receiving, on a first input, a value representative of the potential of the node
    20 retention (N) and, on a second input, a value representative of the target value, an output of the amplifier (8) being connected to apply a voltage to the second terminal of the first capacitor (Cint) ·
    [6" id="c-fr-0006]
    6. Circuit according to the preceding claim, characterized in that
    25 the amplifier (8) is formed by an operational amplifier and in that the output of the operational amplifier feeds the second electrode of the first capacitor (Cint) ·
    [7" id="c-fr-0007]
    7. Circuit according to the preceding claim, characterized in that the circuit
    Polarization 30 (5) applies a first voltage value (Vreset) to the first electrode of the detector (1) during the first period and in that the operational amplifier receives on a first input a voltage (Vamp) offset from said first voltage value (Vreset) of a value equal to the threshold voltage of the transistor (T2) mounted as a follower.
    5
    [8" id="c-fr-0008]
    8. Circuit according to any one of the preceding claims, characterized in that it comprises a second capacitor (Cm) having a first terminal connected to the second terminal of the first capacitor (Cint) and a second terminal connected to a second source of voltage delivering a fixed potential.
    [9" id="c-fr-0009]
    9. Circuit according to any one of the preceding claims, characterized in that it comprises a transfer switch (T4) configured to authorize or block the passage of electric charges between the second electrode of the first capacitor (Cint) and the circuit ( 6) of
    15 transfer.
    [10" id="c-fr-0010]
    10. Circuit according to any one of the preceding claims, characterized in that it comprises a measurement switch (T3) connected between the measurement circuit (7) and the transfer circuit (6).
    [11" id="c-fr-0011]
    11. Circuit according to one of claims 9 and 10, characterized in that the measurement switch (T3) and / or the transfer switch (T4) are formed by a field effect transistor.
    25
    [12" id="c-fr-0012]
    12. Circuit according to one of claims 9 to 11, characterized in that the transfer switch (T4) and the measurement switch (T3) receive the same synchronization signal (SEL rn ) on their control electrode.
    [13" id="c-fr-0013]
    13. Circuit according to one of claims 9 to 12, characterized in that it
    30 comprises a control circuit configured to activate the charge transfer circuit (6) at least twice during the second period, the control circuit being configured to block the transfer of charge between two consecutive phases of activation of the circuit (6 ) charge transfer.
    [14" id="c-fr-0014]
    14. The circuit of claim 13, characterized in that the circuit of
    5 command is configured to switch the transfer switch (T4) to the blocking state between the two consecutive phases of activation of the charge transfer circuit (6).
    [15" id="c-fr-0015]
    15. Detection matrix comprising a plurality of detection circuits
    10 according to any one of claims 1 to 14 organized in rows and columns.
    [16" id="c-fr-0016]
    16. Detection matrix according to claim 15, characterized in that the bias circuits (3) of the detection circuits receive the same
    15 first synchronization signal (RSELrn).
    [17" id="c-fr-0017]
    17. Detection matrix according to one of claims 15 and 16, characterized in that a transfer circuit (6) is common to a plurality of detection circuits.
    [18" id="c-fr-0018]
    18. Detection matrix according to claim 17, characterized in that the bias circuits (5) of a row or of a column of detection circuits are connected to a control circuit configured to effect a simultaneous switching between the first period and the second period
    And in that the control circuit and the transfer circuit (6) are configured to sequentially transfer the charges from the retention nodes (N) of said detection circuits during the second period.
    1/3
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    同族专利:
    公开号 | 公开日
    FR3059189B1|2018-12-07|
    US10458842B2|2019-10-29|
    EP3324610A1|2018-05-23|
    IL255798A|2021-01-31|
    IL255798D0|2017-12-31|
    EP3324610B1|2019-09-11|
    US20180143072A1|2018-05-24|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    EP2600125A1|2011-11-29|2013-06-05|Société Française de Détecteurs Infrarouges - SOFRADIR|Radiation-detection device with improved illumination range|
    WO2013083889A1|2011-12-08|2013-06-13|Societe Francaise De Detecteurs Infrarouges - Sofradir|Device for detecting pulsed electromagnetic radiation|
    JP5324947B2|2009-02-03|2013-10-23|浜松ホトニクス株式会社|Signal processing apparatus and light detection apparatus|KR20180068720A|2016-12-14|2018-06-22|삼성전자주식회사|Event-based sensor and sensing method|
    DE102018130006A1|2018-11-27|2020-05-28|Instrument Systems Optische Messtechnik Gmbh|Device and method for measuring semiconductor-based light sources|
    CN111337905B|2020-03-20|2021-12-28|东南大学|Dual-mode focal plane pixel-level circuit based on CTIA and implementation method|
    法律状态:
    2017-11-28| PLFP| Fee payment|Year of fee payment: 2 |
    2018-05-25| PLSC| Search report ready|Effective date: 20180525 |
    2019-11-26| PLFP| Fee payment|Year of fee payment: 4 |
    2020-05-08| CD| Change of name or company name|Owner name: LYNRED, FR Effective date: 20200401 |
    2021-08-06| ST| Notification of lapse|Effective date: 20210705 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1661322|2016-11-21|
    FR1661322A|FR3059189B1|2016-11-21|2016-11-21|DETECTION CIRCUIT WITH LOW FLOW AND LOW NOISE.|FR1661322A| FR3059189B1|2016-11-21|2016-11-21|DETECTION CIRCUIT WITH LOW FLOW AND LOW NOISE.|
    EP17201545.5A| EP3324610B1|2016-11-21|2017-11-14|Low-flow and low-noise detection circuit|
    US15/818,220| US10458842B2|2016-11-21|2017-11-20|Low flux and low noise detection circuit|
    IL255798A| IL255798A|2016-11-21|2017-11-21|Low flux and low noise detection circuit|
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